Microcircuit packages are known for containing a semiconductor device or circuit but are relatively costly to achieve acceptable levels of reliability and performance. The manufacturing goal is to produce a microcircuit package having a high performance at a low cost. However, microcircuit packages of presently known construction cannot achieve intended performance levels at a low cost. In general, known microcircuit packages employ a ceramic material to provide high thermal performance and high reliability.
To achieve low cost, high thermal performance and high reliability for a microcircuit package which will contain a semiconductor device or circuit, the following criteria should be met:                1. High thermal conductivity in a low cost base material;        2. Low cost insulator material with a thermal coefficient of expansion (TCE) match to the base material; and        3. High thermal performance die attach.        
Many high performance microcircuit packages are fabricated using ceramic dielectric materials with thermal dissipation structures using “flanges” of materials which have matched TCEs. Typical materials incorporated into ceramic packages as flanges include copper-tungsten, copper/molybdenum clad structures, and aluminum-silicon carbide (AlSiC). These materials have an advantage of TCEs fairly close to that of the semiconductor devices. Semiconductor devices typically have thermal coefficients of expansion in the range of 2.8-4.0 ppm/° C. The aforementioned flange materials have TCE values in the range of 6.0-10.0 ppm/° C. TCE values below 10.0 ppm/° C. are desirable so that expansion and contraction during temperature extremes do not cause high levels of stress to the semiconductor device which can cause the device to crack. The deficiencies in these materials are that the thermal conductivities are fairly low, i.e., in the range of 150-240 W/mK (Watt per meter Kelvin), and the cost of these materials is high.
A better flange material would be copper or a copper alloy for at least the following reasons. Copper is a material which is commonly available, has a low cost, and can be fabricated using high volume manufacturing techniques such as stamping. Also, copper and copper alloys have a thermal conductivity in the range of 350-400 W/mK. A technical barrier to using copper for flanges in these applications has been the fact that copper and copper alloys have a high TCE (about 17-20 ppm/° C.). This large difference between the TCEs of copper and that of semiconductor devices has resulted in large stresses applied to the semiconductor devices which can cause a failure during operation. In addition, conventional dielectric materials used for this application are ceramic based. The ceramic material has a TCE in the range of about 6-8 ppm/° C., and the combination of the traditional ceramic dielectric and copper flange result in a large mismatch of TCE and results in excessive warpage or cracking of the dielectric.
To minimize the effects of large stresses being applied to the semiconductor devices in conventional packages having copper flanges, one prior art approach employs an adhesive for the die attach. This allows use of a more ductile die attach but has a substantial drawback in that the adhesive has a very low thermal conductivity which limits the performance of the die attach. Another prior art approach uses high lead solder for the die attach, which allows use of a more ductile solder, but the high lead solder is a problem due to environmental issues. A further prior art approach uses a thick layer of gold, typically 300 micro-inches, applied to the backside of the semiconductor die, which allows for a buffer layer of gold on the die, but the thick layer of gold adds considerable cost to the product. A gold layer has been used on the backside of a gallium arsenide die which is soldered with AuSn eutectic solder to a copper substrate, but this approach has traditionally been limited to small devices <3 mm on a side, and has been limited to devices which have a substantially square shape.
As previously noted, the TCE mismatch between the semiconductor device and the flange material results in failure of the semiconductor device or the die attach by reason of the stress induced by the TCE mismatch. In addition, when a ceramic dielectric material is used with a copper flange, the mismatch in TCE between ceramic and copper can cause large stresses to be developed in the structure, which results in excessive warpage or cracking of the dielectric. When the semiconductor device is soldered to the flange, the temperature of the solder at a liquidus point is 280° C. for gold-tin alloys, or 368° C. for a gold-silicon eutectic composition. For these eutectic compositions, the solder turns into a solidus at the aforementioned temperatures. At this solidus point a top layer of the flange material is frozen, and cooling to room temperature causes a bottom portion of the flange to contract more than the top portion, causing the flange to bend into a concave shape. This concave shape subjects the semiconductor device to a bending stress, and such a tensile stress in the semiconductor device can cause a failure of the device.